In electronic parts, such as a semiconductor device, and the like, a delay locked loop (DLL) circuit is used in order to obtain a desired delay. For example, using a DLL circuit, a delayed signal is produced such that a clock signal is shifted by a desired phase. Then a data signal latched by the delayed signal is selectively output so that it becomes possible to output high-speed serial data. A digital DLL circuit, which is one form of DLL circuits, has a delay line to which a plurality of delay elements are connected in series, and the amount of delay is adjusted by adjusting the number of stages of the delay elements in the delay line.
Also, it is known that a delay element including a differential input transistor, an analog control transistor circuit, and a digital control transistor circuit is disposed on a delay line so that a delay time of the delay element on the delay line is adjusted by an analog control voltage. A differential input clock signal is applied to the differential input transistor. One end of the analog control transistor circuit is connected to a power supply end, and the analog control transistor circuit adjusts the amount of fine delay in response to the analog control voltage. The digital control transistor circuit is connected between the analog control transistor circuit and the differential input transistor, and the digital control transistor circuit adjusts the amount of coarse delay in response to a digital code.
A phase-locked loop circuit capable of operating at a wide range of frequencies, that is to say, from a low-speed transmission system having a frequency of about a few Gbps to a high-speed transmission system having a frequency of about tens of Gbps, is desired. In a phase-locked loop circuit capable of operating at a wide range of frequencies, a problem might occur with a relationship between delay sensitivity, which is a ratio of the amount of change in the control voltage controlling the delay time of the voltage controlled oscillator (VCO), and jitter characteristics. That is to say, if an attempt is made to achieve sufficient delay sensitivity at the time of low-speed transmission, jitter characteristics might be deteriorated at the time of high-speed transmission. Also, if an attempt is made to have good jitter characteristics at the time of high-speed transmission, sufficient delay sensitivity might not be achieved at the time of low-speed transmission.
The followings are reference documents.    [Document 1] Japanese Laid-open Patent Publication No. 2007-97140,    [Document 2] Japanese National Publication of International Patent Application No. 7-502394, and    [Document 3] Japanese Laid-open Patent Publication No. 2013-46271.